1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming transistor devices having an increased gate width dimension.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NFET transistors and create a compressive stress in the channel region for PFET transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of an NFET transistor would only be formed above the NFET transistors. Such selective formation may be accomplished by masking the PFET transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PFET transistors. Conversely, for PFET transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PFET transistor is formed above the PFET transistors.
FIGS. 1A-1D depict an illustrative prior art transistor 100. FIG. 1B is a plan view of the transistor 100 while FIGS. 1A and 1C are cross-sectional views of the transistor taken as indicated in FIG. 1B. FIG. 1D is an enlarged view of a portion of the transistor 100. As shown in FIGS. 1A-1C, the illustrative transistor 100 is formed above a semiconducting substrate 10 in and above an active area defined by an illustrative isolation structure 11. The transistor 100 generally comprises a gate insulation layer 12, a gate electrode 14, a sidewall spacer 16, a source region 18A and a drain region 18B. The approximate gate length (or channel length) 13 of the transistor 100 is depicted in FIG. 1A, whereas the approximate gate width (or channel width) 15 of the transistor is depicted in FIG. 1C.
Various materials of construction and techniques may be employed in forming the illustrative transistor 100. For example, the gate insulation layer 12 may be comprised of a variety of different materials, such as, for example, silicon dioxide, a so-called high-k (k greater than 10) insulation material, etc. Similarly, the gate electrode 14 may also be of a material such as polysilicon or amorphous silicon, or it may be comprised of one or more metal layers that act as the gate electrode 14. The gate electrode structure for the transistor 100 may be made using either so-called “gate-first” or “gate-last” techniques.
FIG. 1D is an enlarged view of a portion of the transistor 100 wherein the gate insulation layer 12 and the gate electrode 14 pass over the isolation structure 11. In one illustrative embodiment, the isolation structure 11 is a trench isolation structure that is performed using well-known techniques. Typically, a pad oxide layer (not shown) will be formed on the substrate 10 followed by the formation of a so-called pad nitride layer (not shown) on the pad oxide layer. The pad nitride layer is then patterned (using a patterned photoresist mask) to define a patterned hard mask. An etching process is then performed through the patterned hard mask to define a trench in the substrate 10. An insulating material, such as silicon dioxide, is then blanket deposited across the substrate 10 so as to over-fill the trench. A chemical mechanical polishing (CMP) process is then performed using the patterned hard mask layer as a polish stop layer to remove the insulating material that is positioned outside of the trench. The patterned hard mask is then removed. The resulting isolation structure 11, a so-called shallow trench isolation (STI) structure, is formed in the substrate 10 and it serves to electrically isolate the transistor 100 from other devices.
Although not depicted in FIGS. 1A-1D, due to the manner in which the isolation structure 11 is formed, the upper surface of the isolation structure 11 is typically above the surface 10S of the substrate 10. Ultimately, the transistor 100 will be subjected to many additional processing operations, such as etching and cleaning operations, which consume some of the isolation structure 11. As shown in FIG. 1D, these cleaning and etching processes result in so-called illustrative “divots” 21 in the isolation structure 11. In some cases, such divots 21 may have a depth 23 of about 1-2 nm, depending on the particular application. Depending upon the extent and location of such divots 21, the isolation function provided by the isolation structure 11 may be compromised. Ideally, none of the isolation structure 11 would be consumed in subsequent processing operations, however, that is not the case in real-world semiconductor manufacturing operations.
The present disclosure is directed various methods of forming transistor devices having an increased width dimension.